1. Field of Invention
The present invention relates to a method of manufacturing metal interconnects. More particularly, the present invention relates to a dual damascene process suitable even for forming metal interconnects in low k dielectrics.
2. Description of Related Art
In the manufacturing of very large scale integrated (VLSI) semiconductors, multilevel interconnects, fabricated from two or more metal interconnect layers above a wafer, are quite common. The purpose of having multilevel interconnects is to increase three-dimensional wiring line structures so that the densely packed devices can be properly linked together. In general, the first layer of wiring lines can be made from polysilicon or a metal, and can be used to electrically couple the source/drain regions of devices in the substrate. In other words, through the formation of vias, devices in the substrate are electrically connected together. For connecting more devices, a second or more layers of metallic wiring can be used. With the increase in level of integration, a parasitic capacitance effect between metallic lines, which can lead to RC delay and cross talk between metallic lines, will increase correspondingly. Consequently, speed of conduction between metallic lines will be slower. Therefore, to reduce the parasitic capacitance effect, a type of low-k organic dielectric material is now commonly used for forming inter-layer dielectric or inter-metal dielectric (ILD/IMD) layers. The low-k organic dielectric material is quite effective in reducing RC delay between metallic lines. In practice, however, there are a number of technical problems regarding the use of low-k organic dielectric that still need to be addressed.
FIGS. 1A through 1E are cross-sectional views showing the progression of manufacturing steps for forming a via according to a conventional method. First, as shown in FIG. 1A, a semiconductor substrate 10 is provided. The substrate already has a metallic wire structure 12 formed thereon. Next, a dielectric layer 14 is deposited over the substrate 10 and the metal wire structure 12 using a chemical vapor deposition (CVD) method. The dielectric layer 14 can be made from a material that includes, for example, a low-k dielectric and preferably has a thickness of 7000-10000 .ANG..
Next, as shown in FIG. 1B, a silicon dioxide layer 16 used as a hard mask is deposited over the dielectric layer 14. The silicon dioxide layer 16 functions as a stop layer and a hard mask in subsequent etching operations.
Next, as shown in FIG. 1C, photolithographic and etching processes are used to pattern the silicon dioxide layer 16. Patterning of the silicon dioxide layer 16 involves the steps of forming a photoresist layer 18 over the silicon dioxide layer 16 and then defining and developing a required pattern on the photoresist layer 18. Finally, using the photoresist layer 18 as a mask, the silicon dioxide layer 16 is etched to form an opening in a position above the metal wire 12.
Next, as shown in FIG. 1D, etching is continued to form a via opening 19 in the dielectric layer 14, so that the via exposes the metal wire 12. This via opening 19 has rather steep sidewalls 15.
Finally, as shown in FIG. 1E, the photoresist layer 18 is removed using plasma that contains oxygen (O.sub.2). The oxygen plasma ashing is isotropic. Since the dielectric layer 14 is made from a carbon-containing organic polymer, the dielectric layer 14 has properties very similar to the photoresist layer 18. Therefore, a portion of the exposed sidewalls 15 will be removed, forming recess cavities 15a on the sidewalls during the oxygen plasma ashing operation.
At present, a method of forming metal interconnects known as dual damascene process is rapidly being developed. FIGS. 2A through 2D are cross-sectional views showing the progression of manufacturing steps in producing a metal interconnect by a conventional dual damascene process.
First, as shown in FIG. 2A, a semiconductor substrate 20 is provided. The substrate 20 already has a metallic wire structure 21 formed thereon. Next, a dielectric layer 22 is deposited over the substrate 20, where the dielectric layer 22 can be made from a low-k dielectric material. Thereafter, a thin silicon dioxide layer 23 is deposited over the dielectric layer 22. The silicon dioxide layer 23 serves as an etching stop layer and a mask in subsequent etching operation. Then, the silicon dioxide layer 23 is etched to form a via opening 24 located above the metal wire structure 21.
Next, as shown in FIG. 2B, another dielectric layer 25 is deposited over the silicon dioxide layer 23. The dielectric layer 25 is preferably made from a low-k dielectric material that has etching properties different from those of the silicon dioxide layer 23. The dielectric layer 25 has a thickness roughly the same as the thickness of the second metallic wiring layer.
Next, as shown in FIG. 2C, photolithographic and etching processes are carried out to form a via 26 and a trench 27 in the dielectric layer 25. Since the silicon dioxide layer 23 can act as an etching stop layer, the etching of the trench 27 stop when the silicon dioxide layer 23 is reached. However, since there is an opening 24 in the silicon dioxide layer 23, etching will continue down the via 26 to expose the metal wire 21. Eventually, a via that links up with the metal wire 12 is formed.
In FIG. 2D, a preliminary metal layer (not shown) is deposited over the substrate 20 to at least fill the dual vias 26, 26a and the trench 27 of FIG. 2C. The preliminary metal layer is then polished by chemical-mechanical polishing (CMP) process to removed the top portion so that the preliminary metal layer becomes the metal layer 26b and the metal layer 27a filling the trench 27. The metal layer 26b is electrically coupled to the metal wire 21. Another metal wire layer (not shown) can be formed on the dielectric layer 25 and is electrically coupled to the metal wire 21 through the metal layer 26b.
However, the above dual damascene process still has a number of defects. For example, because the dielectric layer is formed from a low-k organic dielectric material, the dielectric layer has very low resistance against oxygen plasma etching during the process of removing the photoresist layer. Therefore, recess cavities will similarly be formed on the sidewalls of via 26 just like the recess cavities 15a formed on the sidewalls of via 19 in FIG. 1E.
In light of the foregoing, there is a need to improve dual damascene process for forming metal interconnects.